In the population of integrated circuit chip carriers, including thermal conductive modules, ceramic substrates, and polymeric substrates, it is necessary to minimize the shipment of modules with defective integrated circuit chips, while minimizing the cost of testing and replacement.
Integrated circuit are subjected to various wafer level tests during various stages of fabrication prior to dicing. However, after dicing it is particularly difficult and expensive to test integrated circuit chips. One reason is that an integrated circuit chip must be tested through its pins and pads before populating of the carrier, card, board, or the like.
In populating a card, board or other packages integrated circuit chips are attached to a circuit card or board, e.g., by solder bonding, controlled collapse chip connect, wire lead bonding, or the like. The chip is then tested as part of an assembly, e.g., electrically tested and logically tested. Some of the tests are subtle, for example tests for active and passive pattern faults and "stuck at 1" or "stuck at 0" faults. When a fault is found, the chip is removed from the card or board. This is not a simple "desoldering" step, especially in the case of high I/O density chips, encapsulation chip connect technologies, and multi-chip modules, where the chip must be removed, the chip site redressed, and a new chip installed for testing. In the case of a polymeric substrate, redressing the chip site might include milling.